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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2002 - 2004, zarlink semiconductor inc. all rights reserved. features ? single chip synthesized broadband solution ? configurable as both up converter and downconverter requirements in double conversion tuner applications ? incorporates 8 programmable mixer power settings ? compatible with digital and analogue system requirements ? cso -65 dbc, ctb -68 dbc (typical) ? extremely low phase noise balanced local oscillator, with very low fundamental and harmonic radiation ? pll frequency synthesizer designed for high comparison frequencies and low phase noise ? buffered crystal output for pipelining system reference frequency ?i 2 c controlled applications ? double conversion tuners ? digital terrestrial tuners ? cable telephony ? cable modems ?matv description the sl2101 is a fully integrated single chip broadband mixer oscillator with low phase noise pll frequency synthesizer. it is intended for use in double conversion tuners as both the up and down converter and is compatible with hiif frequencies up to 1.4 ghz and all standard tuner if output frequenc ies. it also contains a programmable power facility for use in systems where power consumption is important. the device contains all elements necessary, with the exception of local oscillat or tuning network, loop filter and crystal reference to produce a complete synthesized block converter, compatible with digital and analogue requirements. august 2004 ordering information sl2101c/kg/np1p ssop tubes sl2101c/kg/np1q ssop tape & reel sl2101c/kg/np2p ssop* tubes sl2101c/kg/np2q ssop* tape & reel sl2101c/kg/lh2n mlp* trays sl2101c/kg/lh2q mlp* tape& reel * pb free all codes baked and drypacked -40 c to +85 c sl2101 synthesized broadband converter with programmable power data sheet figure 1 - functional block diagram
sl2101 data sheet 2 zarlink semiconductor inc. figure 2 - pin diagram ssop package figure 3 - pin diagram mlp package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 xtal cap sda scl bufref vccd vee vee rf rfb vee vccrf vee ifoutputb pump drive port p0 vee add vee vcclo lob lo vcclo vee vee ifoutput xtal vcclo np 28 add nc vcclo lob lo vcclo nc nc nc ifoutputb nc ifout nc vcclo vccd nc nc rf rfb nc vccrf scl sda xtal pump drive port p0 pin 1 ident vee to pad under package 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 xtal cap
sl2101 data sheet 3 zarlink semiconductor inc. quick reference data all data applies at maximum power setting with the following conditions unless otherwise stated; a) nominal loads as follows; 1220 mhz output load as in figure 4 44 mhz output load as in figure 5 b) input signal per carrier of 63 db v *dbm assumes a 75 ? characteristic impedance, and 0 dbm = 109 db v functional description the sl2101 is a broadband wide dynamic ra nge mixer oscillator with on-board i 2 c bus controlled pll frequency synthesizer, optimized for a pplication in double conversi on tuner systems as both the up and down converter. it also has application in any system where a wide dynamic range broadband synthesized frequency converter is required. the sl2101 is a single chip solution containing all necessa ry active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaini ng network. the pin assignment is contained in figures 2 and 3 for the ssop and mlp packages and the block diagram in figure 1. the device also contains a programmable facility to adj ust the power in the lna/mixer so allowing power to be traded against intermodulation performance for power cr itical applications, such as telephony modems. characteristic units rf input operating range 50-1400 mhz input noise figure, ssb, 50-860 mhz 860-1400 6.5 - 8.5 8.5 - 12 db db conversion gain 12 db ctb (fully loaded matrix) -68 dbc cso (fully loaded matrix) -65 dbc p1 db input referred 110 db v local oscillator phase noise as upconverter ssb @ 10 khz offset ssb @ 100 khz offset -90 -112 dbc/hz dbc/hz local oscillator phase noise as downconverter ssb @ 10 khz offset ssb @ 100 khz offset -93 -115 dbc/hz dbc/hz local oscillator phase noise floor -136 dbc/hz pll spurs on converted output with input @ 60 db v<-70 dbc pll maximum comparison frequency 4 mhz pll phase noise at phase detector -152 dbc/hz
sl2101 data sheet 4 zarlink semiconductor inc. converter section in normal application the rf input is interfaced thro ugh appropriate impedance matching and an agc front end to the device input. the rf input preampli fier of the device is designed for low noise figure, within the operating region of 50 to 1400 mhz and for high intermodul ation distortion intercept so offeri ng good signal to noise plus composite distortion spurious performance when loaded with a multi ca rrier system. the preamplifier also provides gain to the mixer section and back isolation from the local oscillator section. the lna/mixer current and hence signal handling and devic e power consumption are programmable through the i 2 c bus as tabulated in figure 7. the typical rf input impedance and matching network fo r broadband upconversion are contained in figures 8 and 9 respectively and for narrow band downconversion in fi gures 10 and 11 respectively. the input referred two tone intermodulation test condition spectrum at maximum power setting is shown in figure 12. the typical input nf and gain versus frequency and nf specification limits, over se lectable power settings are contained in figures 13, 14 and 15 respectively. the output of the preamplifier is fed to the mixer section which is optimized for low radiation application. in this stage the rf signal is mixe d with the local oscillator fr equency, which is generated by the on-board oscillator. the oscillator block uses an external tuneable network and is optimized for low phase noise. the typical oscillator application as an upconverter is shown in figure 16 and the typical phase noise performance in figure 17. the typical oscillator application as a down converter is shown in figure 18, and the phase noise performance in figure 19. this oscillator blo ck interfaces direct with the internal pll to allow for freq uency synthesis of the local oscillator. finally the output of the mixe r provides an open collector differential output drive. the device allows for selection of an if in the range 30-1400 mhz so covering standard hi ifs between 1 and 1.4 ghz and all conventional tuner output ifs. when used as a broadband upconverter to a hiif the output should be differ entially loaded, for example with a differential saw filter, to ma ximize intermodulation performance. a nominal load in maximum power setting is shown in figure 4, which will typically be terminated wi th a differential 200 load. when used as a narrowband downconverter the output should be differentially loaded with a discrete differential to single ended converter as in figure 5, shown tuned to 44 mhz if. alternatively loading can be direct into a differential input amplifier or sawf, in which case external loads to vcc will be required. an example load for 44 mhz application with a gain of 16 db is contained in figure 6. the nf and gain with recommended lo ad versus power setting are contained in figure 20. the typical if output impedance as upconverter and downconverter are contained in figures 21 and 22 respectively. in all applications care should be taken to achieve symmetr ic balance to the if outputs to maximize intermodulation performance. the typical key performance data at 5v vcc and 25 deg c ambient are shown in the section 'quick reference data'. pll frequency synthesizer the pll frequency synthesizer section co ntains all the elements necessary, with the exception of a reference frequency source and loop filter to c ontrol the oscillator, so forming a co mplete pll frequency synthesized source. the device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop wi th good phase noise performance. the lo signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier interfaces direct with the 15-bit fully programmable divider. the programmable divider is of mn+a archit ecture, where the dual modulus prescale r is 16/17, the a counter is 4-bits, and the m counter is 11 bits. the output of the programm able divider is fed to the phase comparat or where it is compared in both phase and frequency domain with the comparison frequency. this fr equency is derived either from the on-board crystal controlled oscillator or from an external reference source. in both cases the referenc e frequency is divided down to
sl2101 data sheet 5 zarlink semiconductor inc. the comparison frequency by the reference divider which is pr ogrammable into 1 of 29 ratios as detailed in figure 23. typical applicat ions for the crystal o scillator are contained in figure 24 and figure 25. fi gure 25 is used when driving a second sl2101 as a downconverter. the output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integr ates the current pulses into the varactor line voltage, used for controlling the oscillator. the programmable divider output fpd divided by two an d the reference divider output fcomp can be switched to port p0 by programming the device into test mode. the test modes are described in figure 26. the crystal reference frequency can be switched to bufr ef output by bit re as described in figure 27. the bufref output is not available on the mlp package. programming the sl2101 is controlled by an i 2 c data bus and is compatible with both standard and fast mode formats. data and clock are fed in on the sda and sc l lines respectively as defined by i 2 c bus format. the device can either accept data (write mo de), or send data (read mode). the lsb of t he address byte (r/w) sets the device into write mode if it is low, and read mode if it is high. tabl es 1 and 2 in figure 28 illustrate the format of the data. the device can be programmed to respond to several addresses, which enables the use of more than one device in an i 2 c bus system. figure 28, table 3 shows how the address is selected by applying a voltage to the 'add' input. when the device receives a valid address byte, it pulls the sda line low during the acknowledge period, and during following acknowledge periods after further data bytes ar e received. when the device is programmed into read mode, the controller accepting the data must pull the sda line low during all status byte acknowledge periods to read another status byte. if the controller fails to pull the sda line low during this peri od, the device generates an internal stop condition, whic h inhibits further reading. write mode with reference to figure 28, table 1, bytes 2 and 3 contain frequency information bits 2 14 -2 0 inclusive. byte 4 controls the synthesizer reference divider ratio, see figure 23 and the charge pump setting, see figure 29. byte 5 controls the test modes, see figure 26, the buffere d crystal reference output sele ct re, see figure 27, the power setting, see figure 7 and the output port p0. after reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0 ' indicating byte 2, and a logic '1' indicating byte 4. having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. having received two complete data bytes, additional data by tes can be entered, where byte interpretation follows the same procedure, without re-addres sing the device. this procedure continues until a stop condition is received. the stop condition can be generated after an y data byte, if however it occurs during a byte transmission, the previous byte data is retained. to fa cilitate smooth fine tuning, th e frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a stop condition. read mode when the device is in read mode, the status byte read from the device takes the form shown in figure 28, table 2. bit 1 (por) is the power-on reset indicator, and this is set to a logic '1' if the vcc supply to the device has dropped below 3v (at 25 c), e.g., when the dev ice is initially turned on. the por is reset to '0' when the read sequence is terminated by a stop command. when por is set high th is indicates that the programmed information may have been corrupted and the device reset to the power up condition. bit 2 (fl) indicates whether the synthesizer is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked.
sl2101 data sheet 6 zarlink semiconductor inc. programmable features synthesizer programmable divi der function as described above reference programmable divider function as described above. charge pump current the charge pump current can be programmed by bits c1 & c0 within data byte 4, as defined in figure 29. power setting the device power and hence signal handling can be programmed by bits i2 - i0 within data byte 5, as defined in figure 7. in all power settings the synthesizer remains enabled to facilitate rapid pll lock reacquisition test mode the test modes are defined by bits t2 - t0 as described in figure 26. general purpose ports, p0 the general purpose port can be programmed by bits p0; logic '1' = on logic '0' = off (high impedance) - this is the default state at device power on buffered crystal reference output, bufrefthe buffered crystal reference frequency can be switched to the bufref output by bit re as described in figure 27. the bufref output defaults to the 'on' conditi on at device power up. this output is only available on the ssop package. figure 4 - nominal output load as upconverter into differential sawf 15 14 10nh 10nh vcc sl2101 output outputb 200 ? 200 ? sawf 33 ? 33 ?
sl2101 data sheet 7 zarlink semiconductor inc. figure 5 - nominal output load as downconverter, 44 mhz if figure 6 - output load as downco nverter to a diffe rential amplifier i2 i1 i0 supply current in ma typ. max. 0 0 0 90* 120 001 67 89 010 56 75 011 51 68 1 0 0 82 109 101 59 78 110 48 64 111 43 57 figure 7 - supply current * default setting on sl2101 output 15 pf 15 pf 10 uh 820 nh 820 nh 10 nf 15 14 sl2101 vcc output 15 14 sl2101 10 nf 10 nf outputb vcc 680 nh 680 nh 100 nf
sl2101 data sheet 8 zarlink semiconductor inc. figure 8 - typical rf input impedance as broadband upconverter (maximum power setting) figure 9 - rf input impedance matching network as 50 - 860 mhz upconverter ch1 s 11 1 u fs start 1 000.000 000 mhz stop 1 400.000 000 mhz db1 4.7v cor avg 16 smo prm z 0 50 27 jul 2001 11:24:54 1 2 3 4 1_: 4.3164 -99.426 1.6007 pf 1 000.000 000 mhz 2_: 3.7266 -80.117 1.15 ghz 3_: 4.1328 -70.223 1.25 ghz 4_: 4.7617 -58.166 1.4 ghz 200 ? 100nf 100nf 47nh 9 10 rfinput rfinputb sl2101 rfin 75 ?
sl2101 data sheet 9 zarlink semiconductor inc. figure 10 - typical rf input impedance as narrow band downconverter (maximum power setting) figure 11 - rf input impedance matching network as 1.22 ghz downconverter ch1 s 11 1 u fs start 1 000.000 000 mhz stop 1 400.000 000 mhz ua6 4.7v cor avg 16 smo prm z 0 75 27 jul 2001 09:05:31 1 2 3 4 1_: 20.07 -46.965 3.3888 pf 1 000.000 000 mhz 2_: 19.795 -34.527 1.15 ghz 3_: 20.666 -26.233 1.25 ghz 4_: 25.772 -15.155 1.4 ghz 2.7pf 10nf 3.9nh 9 10 rfinput rfinputb sl2101 rfin 200 ?
sl2101 data sheet 10 zarlink semiconductor inc. figure 12 - two tone intermodulation test condition spectrum, input referred figure 13 - input nf, typical (maximum power setting) 48 dbuv 94 dbuv c b d 6 4 - 3 m i i f2-f1 f1-df f2+df f1 f2 df 47 dbuv c b d 7 4 - 2 m i i 0 1 2 3 4 5 6 7 8 0 100 200 300 400 500 600 700 800 900 input frequency (mhz) ) b d ( e r u g i f e s i o n
sl2101 data sheet 11 zarlink semiconductor inc. figure 14 - conversion gain as upconverter (maximum power setting) figure 16 - upconverter oscillator application i2 i1 i0 typ nf (db) gain (db) typ cso* (dbc) typ ctb* (dbc) typ ipip2 (db v) typ ipip3 (db v) 0 0 0 6.8 10.1 -65 -65 144 121 0 0 1 6.0 9.1 -60 -54 141 114 0 1 0 5.8 7.6 -56 -42 132 108 0 1 1 6.5 5.4 -49 -35 129 106 1 0 0 8.7 10.4 -63 -60 146 117 1 0 1 6.2 10.0 -64 -56 142 113 1 1 0 5.9 8.3 -58 -42 133 106 1 1 1 6.4 5.8 -50 -34 126 103 figure 15 - upconverter gain, nf and intermodulation with recommended load versus power setting * measured with 128 channels at +7 dbmv. 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800 900 input frequency(in mhz) ) b d n i ( n i a g n o i s r e v n o c gain 11 1 k ? varactor line bb555 2 pf bb555 3x2.75 mm (centre) 3x1.5 mm 3x0.5 mm
sl2101 data sheet 12 zarlink semiconductor inc. figure 17 - oscillator typical pha se noise performance at 10 khz offset figure 18 - downconverte r oscillator application figure 19 - typical phase noise perfor mance as downconverter at 10 khz offset -95 -93 -91 -89 -87 -85 0 100 200 300 400 500 600 700 800 900 ) z h / c b d n i ( e s i o n e s a h p pn 4.3 nh 1 k ? varactor line 2.5 pf bb555 20 21 80 82 84 86 88 90 92 94 96 98 100 1040 1060 1080 1100 1120 1140 1160 1180 1200 2201 lo frequency ) t e s f f o z h k 0 1 t a ( e s i o n e s a h p
sl2101 data sheet 13 zarlink semiconductor inc. figure 21 - typical if output impedance as upconverter, single-ended i2 i1 i0 typ nf (db) gain (db) typ ipip3 (db v) 0 0 0 10.3 15.6 124 0 0 1 9.3 15.1 119 0 1 0 8.8 14.0 112 0 1 1 8.7 12.1 106 1 0 0 11.6 15.4 121.3 1 0 1 9.0 15.1 119.7 1 1 0 8.3 13.9 112.6 1 1 1 8.0 11.9 106.3 figure 20 - downconverter gain, nf and ip3 with recommended (fig. 4) load versus power setting ch1 s 11 1 u fs start 1 000.000 000 mhz stop 1 400.000 000 mhz db1 4.7v cor avg 16 smo prm z 0 50 27 jul 2001 11:24:54 1 2 3 4 1_: 4.3164 -99.426 1.6007 pf 1 000.000 000 mhz 2_: 3.7266 -80.117 1.15 ghz 3_: 4.1328 -70.223 1.25 ghz 4_: 4.7617 -58.166 1.4 ghz
sl2101 data sheet 14 zarlink semiconductor inc. figure 22 - typical if output impedance as downconverter, single-ended r4 r3 r2 r1 r0 ratio 00000 2 00001 4 00010 8 00011 16 00100 32 00101 64 00110 128 00111 256 0 1 0 0 0 illegal state 01001 5 01010 10 01011 20 01100 40 01101 80 01110 160 01111 320 ch1 s 11 1 u fs start 10.000 000 mhz stop 100.000 000 mhz ua6 4.7v cor avg 16 smo prm z 0 50 27 jul 2001 09:48:39 1 2 3 4 1_: 1.3588 k -1.1071 k 7.1882 pf 20.000 000 mhz 2_: 606.87 -695.97 40 mhz 3_: 305.72 -549.5 70 mhz 4_: 213.55 -449.58 100 mhz
sl2101 data sheet 15 zarlink semiconductor inc. figure 23 - reference division ratios figure 24 - standard application 1 0 0 0 0 illegal state 10001 6 10010 12 10011 24 10100 48 10101 96 10110 192 10111 384 1 1 0 0 0 illegal state 11001 7 11010 14 11011 28 11100 56 11101 112 11110 224 11111 448 r4 r3 r2 r1 r0 ratio xtalcap xtal 4 7pf 4mhz 47pf 1 2
sl2101 data sheet 16 zarlink semiconductor inc. figure 25 - application when driving two sl2101 from one crystal figure 26 - test modes * clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle status byte bit fl. note:the bufref output is only available on the ssop package figure 27 - buffered crystal reference output select t2 t1 t0 test mode description 0 0 0 normal operation 0 0 1 charge pump sink * status byte fl set to logic ?0? 0 1 0 charge pump source * status byte fl set to logic ?0? 0 1 1 charge pump disabled * status byte fl set to logic ?1? 1 0 0 normal operation and port p0 = fpd/2 1 0 1 charge pump sink * status byte fl set to logic ?0? port p0 = fcomp 1 1 0 charge pump source * status byte fl set to logic ?0? port p0 = f comp 1 1 1 charge pump disabled * status byte fl set to logic ?1? port p0 = f comp re bufref output 0 disabled, high impedance 1 enabled xtalcap xtal 47pf 47pf 10pf 4mhz 1 2 820nh 10k xtalcap xtal sl2101 upconve rter sl2101 downconve rter 1 2
sl2101 data sheet 17 zarlink semiconductor inc. figure 28 - read/write data formats table 1 - write data format (msb is transmitted first) msb lsb address 1 1 0 0 0 ma1 ma0 0 a byte 1 programmable divider 0 2 14 2 13 2 12 2 11 2 10 2 9 2 8 a byte 2 programmable divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a byte 3 control data 1 c1 c0 r4 r3 r2 r1 r0 a byte 4 control data t2 t1 t0 i2 i1 i0 re p0 a byte 5 table 2 - read data format (msb is transmitted first) a : acknowledge bit ma1,ma0 : variable address bits (see table 3) 2 14 -2 0 : programmable division ratio control bits i2-i0 : lna/mixer power select (see figure 7) c1-c0 : charge pump current select (see figure 29) r4-r0 : reference division ratio select (see figure 23) t2-t0 : test mode control bits (see figure 26) re : buffered crystal reference output enable (see figure 27 p0 : p0 port output state por : power on reset indicator fl : phase lock flag msb lsb address 1 1 0 0 0 ma1 ma0 1 a byte 1 programmable divider por fl 0 0 0 0 0 0 a byte 2 table 3 - address selection ma1 ma0 address input voltage level 0 0 0-0.1vcc 0 1 open circuit 1 0 0.4vcc ? 0.6 vcc # 1 1 0.9 vcc - vcc
sl2101 data sheet 18 zarlink semiconductor inc. figure 29 - charge pump current electrical char acteristics - test conditions (unless otherwise stated). t amb = -40 o to 85 o c, vee= 0v, vcc=5 v+-5%. these characteristics are guaranteed by either production test or desig n. they apply within the specified ambient temperature and sup ply voltage at maximum power setting unless otherwise stated. c1 c0 current in ma min. typ. max. 0 0 +-98 +-130 +-162 0 1 +-210 +-280 +-350 1 0 +-450 +-600 +-750 1 1 +-975 +-1300 +-1625 characteristic pin min. typ. max. units conditions supply current 6, 12,17, 19, 22 90 120 ma if outputs will be connected to vcc through the differential load as in figures 4, 5 & 6. see figure 7 for programmable settings. input frequency range 9, 10 50 1400 mhz operating condition only. output frequency range 14, 15 30 1400 mhz operating condition only. composite peak input signal 9, 10 97 db v operating condition only. all synthesizer related spurs on if output 14, 15 -60 dbc within channel bandwidth of 8 mhz and with input power of 60 db v. upconverter application input frequency range 9, 10 50 860 mhz input impedance 75 ? see figure 8. input return loss 6 db with input matching network as in figure 9. input noise figure 9.5 db ta m b = 2 7 c, see figure 13, with input matching network as in figure 9. see figure 15 for programmable settings. conversion gain 9 db differential voltage gain to 200 ? load on output of sawf as in figure 4, see figure 14. see figure 15 for programmable settings.
sl2101 data sheet 19 zarlink semiconductor inc. gain variation across operation range -1 +1 db 50-860 mhz gain variation within channel 0.5 db channel bandwidth 8 mhz within operating frequency range. through gain -20 db 45-1400 mhz cso -65 dbc measured with 128 channels at 62 db v. see figure 15 for programmable settings. ctb -68 dbc measured with 128 channels at 62 db v. see figure 15 for programmable settings. ipip2 2t 141 dbuv see note 2. see figure 15 for programmable settings. ipip3 2t 117 dbuv see note 2. see figure 15 for programmable settings. ipim2 2t -47 dbc see note 2. see figure 12. ipim3 2t -46 dbc see note 2. see figure 12. lo operating range 1 2.3 ghz maximum tuning range 0.9 ghz determined by application. lo phase noise, ssb @ 10 khz offset @ 100 khz offset -86 -106 dbc/hz dbc/hz application as in figure 16. see figure 17. lo phase noise floor -136 dbc/hz application as in figure 16. if output frequency range 14, 15 1 1.4 ghz if output impedance see figure 21. downconverter application input frequency range 9, 10 1000 1400 mhz input impedance 75 ? see figure 10. input return loss 12 db with input matching network as in figure 11. input noise figure 14 db tamb=27 c, with input matching network as in figure 11. see figure 20 for programmable settings. characteristic pin min. typ. max. units conditions
sl2101 data sheet 20 zarlink semiconductor inc. conversion gain 12 db differential voltage gain to 50 ? load on output of impedance transformer as in figure 6. see figure 20 for programmable settings. gain variation within channel 0.5 db channel bandwidth 8 mhz within operating frequency range. through gain -20 db 45-1400 mhz ipip3 2t 117 db v see note 2. ipim3 2t -46 dbc see note 2. see figure 12. lo operating range 1 2.3 ghz maximum tuning range determined by application, see note 4. lo phase noise, ssb @ 10 khz offset @ 100 khz offset -92 -112 dbc/hz dbc/hz application as in figure 18. see figure 19. lo phase noise floor -136 dbc/hz application as in figure 18. if output frequency range 14, 15 100 mhz if output impedance see figure 22. synthesizer sda, scl 3, 4 input high voltage 3 5.5 v i 2 c ?fast mode? compliant input low voltage 0 1.5 v input high current 10 a input voltage = vcc input low current -10 a input voltage = vee leakage current 10 avcc=vee hysterysis 0.4 sda output voltage 3 0.4 0.6 v v isink = 3 ma isink = 6 ma scl clock rate 4 400 khz charge pump output current 28 see figure 29. vpin = 2 v charge pump output leakage 28 +-3 +-10 na vpin = 2 v characteristic pin min. typ. max. units conditions
sl2101 data sheet 21 zarlink semiconductor inc. note 1: all power levels are referred to 75 ? and 0 dbm = 109 db v note 2: any two tones within rf operating range at 94 db v beating within band, with ou tput load as in figure 4 note 3: port powers up in high impedance state note 4: to maximise phase noise the tuning range should be minimi sed and q of resonator maximised. the application as in figure 18 has a tuning range of 200 mhz. note 5: if the bufref output is not used it should be left open circuit or connected to vccd and disabled by setting re = '0'. charge pump drive output current 27 0.5 ma vpin = 0.7 v crystal frequency 1,2 2 20 mhz see figure24 and figure 25 for application. recommended crystal series resistance 10 200 ? 4 mhz parallel resonant crystal external reference input frequency 2 2 20 mhz sinewave coupled through 10 nf blocking capacitor external reference drive level 2 0.2 0.5 vpp compatible with bufref output. (ssop package only) phase detector comparison frequency 4mhz equivalent phase noise at phase detector ssb, within loop bandwidth -148 dbc/hz f comp = 1 mhz -152 dbc/hz f comp = 250 khz -158 dbc/hz f comp = 62.5 khz local oscillator programmable divider division ratio 240 32767 reference division ratio see figure 23. output port sink current leakage current 26 2 10 ma a see note 3. vport = 0.7 v vport =vcc bufref output output amplitude output impedance 5 0.35 250 vpp ? ac coupled. note 5. enabled by bit re=1 and default state on power-up. bufref output only available on ssop package address select input high current input low current 1 -0.5 ma ma see figure 28, table 3 vin=vcc vin=vee characteristic pin min. typ. max. units conditions
sl2101 data sheet 22 zarlink semiconductor inc. absolute maximum ratings - all voltages are referred to vee at 0 v (pins 7, 8, 11, 13, 16, 18, 23, 25). characteristic pin min. max. units conditions supply voltage, v cc 6, 12, 17, 19, 22 -0.3 6 v rf input voltage 9, 10 117 dbuv differential, ac coupled inputs all i/o port dc offsets -0.3 vcc+0.3 v sda, scl dc offsets 3, 4 -0.3 6 v vcc = vee to 5.25 v storage temperature -55 150 c junction temperature 125 c power applied. package thermal resistance, chip to case (ssop) 20 c/w package thermal resistance, chip to ambient (ssop) 85 c/w power consumption at 5.25 v 630 mw maximum power setting. esd protection (pins 3-28) 1 kv mil-std 883b method 3015 cat1 esd protections (pins 1, 2) 0.75 kv
sl2101 data sheet 23 zarlink semiconductor inc. figure 30 - input and output interface circuits (rf section) rf inputs oscillator inputs if outputs
sl2101 data sheet 24 zarlink semiconductor inc. figure 31 - input and output interface circuits (pll section) v ccd * 120k v ccd p0 v ccd 1 * on sda only 200 a 1ma output port bufref output sda/scl (pins 3 and 4) add input reference oscillator loop amplifier

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